Low-voltage Differential Signaling (LVDS) technology is commonly used to provide a low-power and a low-voltage alternative to other high-speed input/output (I/O) interfaces, specifically for point-to-point transmissions, such as those used in network devices within data and communication networks.
An LVDS receiver is an essential part of an LVDS transceiver that is employed for high-speed low-power differential signaling over electrical interconnects. The high-speed data transmission is widely applied to a variety of applications which may include, but need not be limited to, data transmission between chips, data transmission between integrated circuit boards and the like.
The LVDS receiver has to receive a differential signal ranging from 250 millivolt (mV) to 400 mV while accommodating a large common-mode voltage over which the differential signal ranging from 0.2V to 2.2 V resides. Also, the LVDS receiver has to regenerate this very low-voltage signal into a rail-to-rail high-edge-rate signal.
Thus, an LVDS receiver circuit has to be designed in such a way that it can accommodate a large (2 volt) common-mode input range and providing a high enough gain and bandwidth to regenerate the received low-voltage and low-edge rate signal. Further, the LVDS receiver circuit has to perform the above mentioned functions in a power-efficient and an area-efficient manner.
Conventional LVDS receiver circuit designs employ a folded-cascode operational-transconductance amplifier (OTA) as a first stage of the receiver circuit with a p-type metal oxide semiconductor (PMOS) input pair. The folded-cascode OTA provides a high gain with a targeted bandwidth while the PMOS input pair allows for a high common-mode input range.
The folded-cascode OTA is followed by a domain-shifter circuit that converts the I/O voltage to a core voltage of the receiver chip. As the LVDS receiver is a well-researched domain for integrated circuits, complementary metal oxide semiconductor (CMOS) processes going towards the deep submicron regime and the LVDS receiver circuit design employed with the PMOS input pair and the domain shifter circuit raises new challenges in accordance with the power and area used for the LVDS receiver circuit.
Therefore, in light of the above, there is a need for an LVDS receiver circuit design that further improves gain and bandwidth along with a considerable reduction in area and power consumption.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention.